Bondpad attachments having self-limiting properties for penetration of semiconductor die

ABSTRACT

A die contacting substrate establishes ohmic contact with the die by means of raised portions on contact members. The raised portions are dimensioned so that a compression force applied to the die against the substrate results in a limited penetration of the contact member into the bondpads. The arrangement may be used for establishing electrical contact and with a burn-in oven and with a discrete die tester. This permits the die to be characterized prior to assembly, so that the die may then be transferred in an unpackaged form. A Z-axis anisotropic conductive interconnect material may be interposed between the die attachment surface and the die.

CROSS-REFERENCE TO RELATED APPLICATION

[0001] This is a continuation-in-part to U.S. patent application Ser.No. 7/709,858 filed Jun. 4, 1991, U.S. patent application Ser. No.7/788,065, filed Nov. 5, 1991, and U.S. patent application Ser. No.7,981,956, filed Nov. 24, 1992.

BACKGROUND OF THE INVENTION

[0002] 1. Field of the Invention

[0003] This invention relates to electrical test equipment forsemiconductor devices. More specifically, the invention relates to anapparatus and method, which utilize conductive polymers, and which areused to perform dynamic burn-in and full electrical/performance/speedtesting on discrete nonpackaged or semi-packaged dies.

[0004] 2. Background of the Invention

[0005] Semiconductor devices are subjected to a series of testprocedures in order to assure quality and reliability. This testingprocedure conventionally includes “probe testing”, in which individualdies, while still on a wafer, are initially tested to determinefunctionality and speed. Probe cards are used to electrically test dieat that level. The electrical connection interfaces with only a singledie at a time in wafer; not discrete die.

[0006] If the wafer has a yield of functional dies which indicates thatquality of the functional dies is likely to be good, each individual dieis assembled in a package to form a semiconductor device.Conventionally, the packaging includes a lead frame and a plastic orceramic housing.

[0007] The packaged devices are then subjected to another series oftests, which include burn-in and discrete testing. Discrete testingpermits the devices to be tested for speed and for errors which mayoccur after assembly and after burn-in. Burn-in accelerates failuremechanisms by electrically exercising the devices (DUT) at elevatedtemperatures, thus eliminating potential failures which would nototherwise be apparent at nominal test conditions.

[0008] Variations on these procedures permit devices assembled ontocircuit arrangements, such as memory boards, to be burned-in, along withthe memory board in order to assure reliability of the circuit, aspopulated with devices. This closed assembly testing assumes that thedevices are discretely packaged in order that it can then be performedmore readily.

[0009] If the wafer has a yield of grossly functional die, it indicatesthat a good quantity of die from the wafer are likely to be fullyoperative. The die are separated with a die saw, and the nonfunctionaldie are scrapped, while the rest are individually encapsulated inplastic packages or mounted in ceramic packages with one die in eachpackage. After the die are packaged they are rigorously electricallytested. Components which turn out to be nonfunctional, or which operateat questionable specifications, are scrapped or devoted to special uses.

[0010] Packaging unusable die, only to scrap them after testing, is awaste of time and materials, and is therefore costly. Given therelatively low profit margins of commodity semiconductor components suchas dynamic random access memories (DRAMs) and static random accessmemories (SRAMs), this practice is uneconomical. However, no thoroughand cost effective method of testing an unpackaged die is availablewhich would prevent this unnecessary packaging of nonfunctional andmarginally functional die. Secondly, the packaging may have otherlimitations which are aggravated by burn-in stress conditions, so thatthe packaging becomes a limitation for burn-in testing.

[0011] It is proposed that multiple integrated circuit devices bepackaged as a single unit, known as a multi chip module (MCM). This canbe accomplished with or without conventional lead frames. This createstwo problems when using conventional test methods. Firstly, discretetesting is more difficult because a conventional lead frame package isnot used. Furthermore, when multiple devices are assembled into a singlepackage, the performance of the package is reduced to that of the diewith the lowest performance. Therefore, such dies are tested on anindividual basis at probe, using ambient and “hot chuck” testtechniques, while still in wafer form. In other words, the ability topresort the individual dice is limited to that obtained through probetesting.

[0012] In addition, there is an increased interest in providing partswhich are fully characterized prior to packaging. This is desired notonly because of the cost of the package, but also because there isdemand for multi-chip modules (MCMs), in which multiple parts in dieform are tested and assembled into a single unit. While there arevarious techniques proposed for testing, burning in and characterizing asingulated die, it would be advantageous to be able to “wafer map” thedie prior to assembly with as many performance characteristics aspossible. Ideally, one would want to be able to map the wafer with fulldevice characterization.

[0013] MCMs create a particular need for testing prior to assembly, ascontrasted to the economics of testing parts which are discretelypackaged as singulated parts. For discretely packaged parts, if theproduct yield of good parts from preliminary testing to final shipment(probe-to-ship) is, for example, 95%, one would not be particularlyconcerned with packaging costs for the failed parts, if packaging costsare 10% of the product manufacturing costs. Even where packaging costsare considerably higher, as in ceramic encapsulated parts, testingunpackaged die is economical for discretely packaged parts when theadded costs approximates that of cost of packaging divided by yield:${C_{DIE} \times \frac{C_{PACKAGE}}{Yield}} = {C_{DIE} \times C_{{ADDL}.\quad {KGD}}}$

[0014] where C=cost

[0015] C_(DIE)=manufacturing cost of functional die

[0016] C_(ADDL. KDD)=additional cost of testing unpackaged die in orderto produce known good die (KGD) Note that in the case of discretelypackaged parts, the cost of the die (C_(DIE)) is essentially not afactor. This changes in the case of MCMs:${\left( C_{DIE} \right) \times \frac{\left( {{number}\quad {of}\quad {die}} \right)}{Yield} \times C_{PACKAGE}} = {C_{DIE} \times C_{{ADDL}.\quad {KGD}}}$

[0017] Note that again C_(DIE) is not a factor in modules havingidentical part types; however, the equation must be modified to accountfor varied costs and yields of die in modules with mixed part types.

[0018] With MCMs, the cost of packaging a failed part is proportional tothe number of die in the module. In the case of a x16 memory arraymodule, where probe-to-ship yield of the die is 95%, the costs are:${\frac{16}{0.95} \times C_{PACKAGE}} = C_{{ADDL}.\quad {KGD}}$

[0019] so the additional costs of testing for known good die (KGD) maybe 16 times the cost of testing an unrepairable module and still beeconomical. This, of course, is modified by the ability to repair failedmodules.

[0020] Testing of unpackaged die before packaging into multichip moduleswould be desirable as it would result in reduced material waste,increased profits, and increased throughput. Using only known good diein MCMs would increase MCM yields significantly.

[0021] Testing unpackaged die requires a significant amount of handling.Since the test package must be separated from the die, the temporarypackaging may be more complicated than either standard discretepackaging or multichip module (MCM) packaging. The package must becompatible with test and burn-in procedures, while securing the diewithout damaging the die at the bondpads or elsewhere during theprocess.

[0022] In U.S. Pat. No. 4,899,107, commonly assigned, a reusableburn-in/test fixture for discrete TAB die is taught. The fixtureconsists of two halves, one of which is a die cavity plate for receivingsemiconductor dies as the units under test (UUT); and the other halfestablishes electrical contact with the dies and with a burn-in oven.

[0023] The first half of the test fixture contains cavities in which dieare inserted circuit side up. The die will rest on a floating platform.The second half has a rigid high temperature rated substrate, on whichare mounted probes for each corresponding die pad. Each of a pluralityof probes is connected to an electrical trace on the substrate (similarto a P.C. board) so that each die pad of each die is electricallyisolated from one another for high speed functional testing purposes.The probe tips are arranged in an array to accommodate eight or sixteendies.

[0024] The two halves of the test fixture are joined so that each pad oneach die aligns with a corresponding probe tip. The test fixture isconfigured to house groups of 8 or 16 die for maximum efficiency of thefunctional testers.

[0025] There are some testing and related procedures when the parts aresingulated. For this reason, it is inconvenient to retain multiple diein a single test fixture.

[0026] Various forms of connections are used to connect the die to apackage or, in the case of a multichip module (MCM), to otherconnections. These include wirebonding, TAB connections, bump bondingdirectly to substrate, and conductive adhesives.

[0027] The bondpads are conductive areas on the face of the die whichare used as an interconnect for connecting the circuitry on the die tothe outside world. Normally, conductors are bonded to the bondpads, butit is possible to establish electrical contact through the bondpads bybiasing conductors against the bondpads without actual bonding.

[0028] One of the problems encountered with burn in and fullcharacterization testing of unpackaged die is the physical stress causedby connection of the bondpads to an external connection circuitry. Thisproblem is complicated by the fact that in many die configurations, thebondpads are recessed below the surface level of a passivation layer.The passivation layer is a layer of low eutectic glass, such as BPSG,which is applied to the die in order to protect circuitry on the die.(The term “eutectic” does not, strictly speaking, apply to glass, whichis an amorphous fluid; however, the term is used to describe thecharacteristic of some glasses wherein, as a result of theirformulation, they readily flow at a given temperature.)

[0029] The ohmic contact between bondpads or test points on a die and aknown good die test carrier package has been a matter of interest. It isdifficult to achieve and maintain consistent ohmic contact withoutdamaging the bondpads and passivation layer on the die. The designcriteria of such contacts is somewhat different from the design criteriaof the carrier package.

SUMMARY OF THE INVENTION

[0030] It has been found desirable to perform testing and relatedprocedures in discrete fixtures prior to final assembly. In order toaccomplish this, a reusable burn-in/test fixture for discrete die isprovided. The fixture preferably consists of two halves, one of which isa die cavity plate for receiving a semiconductor die as the units undertest (UUT).

[0031] An intermediate substrate is used to establish ohmic contact withthe die at bondpads or testpoints. The intermediate substrate isconnected to conductors on the reusable test fixture, so that thebondpads or testpoints are in electrical communication with theconductors on the test fixture.

[0032] The intermediate substrate is preferably formed of asemiconductor material, and includes circuitry which is used to conductsignals between bondpad locations and external connector leads on thefixture. The substrate with circuitry is able to establish contact withthe external connector leads, or with other leads on the fixture whichare in communication with the external connector leads. In the preferredembodiment, the substrate is formed from silicon, although othersemiconductor materials may be used. Examples of alternative materialsinclude germanium and silicon on saphire (SOS).

[0033] The substrate is formed with portions having increased height,such as bumps. These bumps, in turn, are formed with raised portions orpoints, so that the raised portion may penetrate the bondpad, while theremainder of the bump functions to limit penetration depth of the raisedportion. This permits the penetration depth of the bump to be controlledby the physical dimensions of the raised portion. This results in thebumps being self-limiting in their penetration of the bondpads.

[0034] In a modification of the invention, a Z-axis anisotropicconductive interconnect material is provided as an interface between thesubstrate and the die. The Z-axis anisotropic conductive interconnectmaterial is used to establish ohmic contact with bondpads or theequivalent attach points on the semiconductor die. The Z-axisanisotropic conductive interconnect material is able to conform to theshape of the die at the bondpad sufficiently to establish the ohmiccontact without substantially damaging the bondpad. Since contact isable to be established by biasing force, it is possible to perform burnin and test of the die without resorting to bonding a conductor to thebondpad.

[0035] The Z-axis anisotropic conductive interconnect material is ametal filled polymer composite which is able to function as a compliantinterconnection material for connector and testing applications. Thismaterial is in a group of materials which are referred to as elastomericconductive polymer interconnect (ECPI) materials. These are availablefrom AT&T Bell Laboratories, of Allentown, Pa., or Shin Etsu PolymerAmerica Inc., of Union City, Calif., 3M Company of Minneapolis, Minn.,at their Austin, Tex. plant or Nitto Denko America, Inc., San Jose,Calif. (a subsidiary of Nitto Denko Corporation of Japan).

[0036] The contact between the bondpads and the external connector leadsis therefore established by utilizing the Z-axis anisotropic conductiveinterconnect material and substrate with circuitry. Conductors on theZ-axis anisotropic conductive interconnect material and substrate withcircuitry extend from the bondpads. to connection points, and theconnection points conduct to contacts, which are in turn incommunication with the external connector leads. The self-limitingnature of the bump is transferred through the Z-axis anisotropicconductive interconnect material so that the potential damage to thebondpad by force exerted through the Z-axis anisotropic conductiveinterconnect material is limited.

[0037] In a preferred embodiment, the intermediate substrate is placedin the die receiving cavity and is electrically connected to conductorson the fixture, which in turn are connected to the connector pins. Thedie is placed face down in the die receiving cavity. The substrate isattached to conductors on the fixture, which in turn are connected tothe connector pins. Ohmic contact is established between bondpads ortestpoints on the die and conductors on the substrate.

[0038] Z-axis anisotropic conductive interconnect material may be placedin the die receiving cavity beneath the die so that the ohmic contactwith the bondpads or testpoints on the die may be established throughthe Z-axis anisotropic conductive interconnect material, through thesubstrate, to communicate with external connector leads on the fixture.

[0039] In an alternate embodiment, a die is placed face up in a cavityin a first half of the fixture, and the semiconductor substrate isplaced over the die. In the preferred form of that embodiment, theexternal connector leads are connector pins, which preferably are in aDIP (dual inline package) or QFP (quad flat pack) configuration. Thepins terminate at the connection points.

[0040] The fixture establishes electrical contact with the a single dieand with a burn-in oven, as well as permitting testing of dies indiscretely packaged form.

[0041] If the die is placed face up in a cavity in a first half of thefixture, the substrate may be placed between the die and a lid.Attachment of the die to the external connection leads is establishedeither through contact points on the substrate, or through the contactpoints through the Z-axis anisotropic conductive interconnect material,in which case, the substrate establishes contact with the Z-axisanisotropic conductive interconnect material.

BRIEF DESCRIPTION OF THE DRAWINGS

[0042]FIGS. 1 and 2 show a preferred embodiment of the inventive burn-infixture;

[0043]FIG. 3 shows details of an intermediate substrate formed ofsilicon according to the invention;

[0044]FIG. 4 shows details of electrical ohmic contact of the substratewith bondpads on a die;

[0045]FIG. 5 shows details of an intermediate substrate formed from aceramic material with conductive traces;

[0046]FIG. 6 shows details of a raised portion of a bump, wherein thebump may be self-limiting in its penetration of the bondpads;

[0047]FIG. 7 shows details of Z-axis anisotropic conductive interconnectmaterial and an intermediate substrate used with one embodiment of theinvention;

[0048]FIG. 8 shows a modification to the embodiment of FIGS. 1 and 2, inwhich a resilient strip is used to bias the die against the intermediatesubstrate;

[0049]FIG. 9 shows a configuration of the invention in which a diereceiving housing is used to retain a die face up;

[0050]FIG. 10 shows a modification of the invention, in which anintermediate substrate is used to directly connect the die to anexternal connector connected to external test circuitry; and

[0051]FIG. 11 shows a configuration in which an intermediate substrateextends over the die and a part of the die cavity plate which includeselectrical contacts.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

[0052] Referring to FIGS. 1 and 2, the inventive burn-in fixture 11includes a die cavity plate, 13 and a cover 15. The die cavity plate 13includes a die receiving cavity 17.

[0053] The die receiving cavity 17 has dimensions which are at leastsufficient to accommodate a die 21. The die 21 is to be connected atbondpads 27, which are typically 0.1 mm wide. The die cavity plate 13has a slot 31 which permits convenient access to the bottom of the die21 in order that the die 21 may be lifted out of the die receivingcavity 17. Alignment of the die 21 in the die cavity plate 13 isachieved by aligning the cover 15 and die 21 to the bondpad 27.

[0054] A plurality of external connector leads 33 extend from the burnin fixture 11. As can be seen in FIG. 2, in the preferred embodiment,the external connector leads 33 are attached to the die cavity plate 13,and extend therefrom. The external connector leads 33 are shown asconnector pins, which preferably are in a DIP (dual inline package) orQFP (quad flat pack) configuration.

[0055] The external connector leads 33 are secured by the die cavityplate 13 and terminate on the die cavity plate 13 with contact pads 37.

[0056] Referring to FIG. 3, as well as FIGS. 1 and 2, an intermediatesubstrate 41 is used to extend between a wire connection to the contactpads 37 on the die cavity plate 13 and the bondpads 27. The intermediatesubstrate 41 includes a plurality of die contacts 43 which establishohmic contact with the bondpads 27 or other test points on the die 21.

[0057] The intermediate substrate 41 is preferably formed of silicon,and includes a plurality of conductive circuit traces 45 thereon whichcommunicate with substrate bondpads 47. The conductive traces 45 arepreferably on a top surface 49 of the intermediate substrate 41. Thesubstrate bondpads 47 are connected to the contact pads 37 by anyconvenient means, such as by wirebond. The use of silicon or othersemiconductor material for forming the intermediate substrate 41 permitsthe contacts 43 and conductive traces 45 to be formed on the substrateby semiconductor circuit fabrication techniques, such as those used toform conductive lines and bondpads on semiconductors integrated circuitdevices.

[0058] The intermediate substrate 41 may be formed as a rigid,semirigid, semiflexible or flexible material. In the case of silicon, asthe substrate material, it is possible to form the material thin enoughthat it is at least semiflexible. In the preferred embodiment, a rigidsubstrate is used.

[0059] In the preferred embodiment, the intermediate substrate 41 issubstantially rigid. The rigidity is sufficient that, when theintermediate substrate 41 is aligned with the die 21, the height of thedie contacts 43 nearly align in a Z axis direction with the bondpads 27and that contact is established between the bondpads 27 and die contacts43 without the need to significantly distort the intermediate substrate41. Typically such contact is achieved at all desired points by allowingthe die contacts 43 to be depressed, or by the use of a Z-axisanisotropic conductive interconnect material (67, FIG. 7).

[0060] The intermediate substrate 41 may also be formed of othersemiconductor process materials such as silicon on saphire (SOS),silicon on glass (SOG) or semiconductor process materials usingsemiconductor materials other than silicon.

[0061] The bondpads, as can be seen in FIG. 4, are typically recessedbelow a top surface level 51, established by a BPSG passivation layer53.

[0062] Alternatively, as shown in FIG. 5, the intermediate substrate 41may be formed from a ceramic material 55 onto which are formed aplurality of conductive traces 59. The conductive traces 59 have bumps61 which are intended for registration with a bondpad 27, or a contactpad should the substrate 41 extend that far. The conductive traces 59therefore are able to conduct signals between the bondpads 27 and thecontact pads 37, provided that ohmic contact is established between thebondpads 27 and contact pads 37 and the respective bumps 61. It is alsopossible to use any other suitable interconnect, including for exampleflexible, rigid or semi-rigid polyimide tape.

[0063] In either the silicon or the ceramic substrate, the conductivetraces and the die contacts 43 (FIG. 3) or the bumps 61 (FIG. 5), may bemade of metal conductors or of any material which has significantconductivity, provided that the conductivity of the element issufficient to permit electrical testing of the die.

[0064] The use of an intermediate substrate 41 allows dies withdifferent patterns of bondpads 27 to be aligned with a version of theintermediate circuit trace substrate 41 custom made for that die, withseveral variants of the intermediate circuit trace substrate 41 matingwith the same die cavity plate 13.

[0065] Since the intermediate substrate 41 also has the die contacts 43thereon, the lifetime of the die contacts 43 is not directlydeterminative of the lifetime of the die cavity plate 13. Also, in thepreferred embodiment, the external connector leads 33 are electricallyconnected to the contact pads 37 by internal conductors 65. The factthat the conductive traces 45 are on the top surface 49 of theintermediate substrate 41 facilitate the formation of elevated contactson the die contacts 43, and allow the use of materials which aresuitable for the formation of the elevated contacts.

[0066] The die 21 is placed on the intermediate substrate 41 withbondpads 27 on the die 21 aligned with the die contacts 43. Raisedasperities 69 are located at the point of contact of the die contacts 43with the bondpads 27. The raised asperities 69 are formed on the diecontacts 43. In the case of a ceramic intermediate substrate, theasperities are formed by a combination of photoplating techniques anddoinking. Other techniques for depositing material may be used in lieuof photoplating, such as stenciling, screen printing or direct writing.The doinking process is described in copending U.S. patent applicationSer. No. 7/898,637, filed Jun. 15, 1993, for PROCESS FOR FORMING RAISEDSURFACE IRREGULARITIES BY ULTRASONIC FORGING, by Alan Wood, DavidHembree and Warren Farnworth, and U.S. Pat. No. 5,249,450 applicationSer. No. 7/898,624 entitled PROBEHEAD FOR ULTRASONIC FORGING, by AlanWood, David Hembree, Larry Cromar and Warren Farnworth. It isanticipated that the intermediate substrate 41 may be repeatedly used,and the die contacts 43 re-doinked between uses.

[0067] As shown on FIG. 6, the bumps 61 on the intermediate substrate 41may be formed with raised portions 73. The raised portion 73 maypenetrate the bondpad 27 or contact pad 37, while the remainder of thebump 61 functions to limit penetration depth of the raised portion 73.This permits the penetration depth of the bump 61 to be controlled bythe physical dimensions of the raised portion 73. This results in thebumps 61 being self-limiting in their penetration of the bondpads 27,since the force required to cause the raised portion 73 to penetrate thebondpad 27 is significantly less than the force required for theremainder of the bump 61 to penetrate the bondpad 27.

[0068] The result is the raised portion 73 causes an indentation in thebondpad 27 but the indentation preferably is less than the thickness ofthe bondpad 27. The remainder of the bondpad beneath the bump 61 may beslightly distorted, but remains fully workable in subsequent assemblyoperations. for subsequent assembly operations, the bondpad 27 may betreated as if it were undamaged, and therefore the bondpad is considerednot to be significantly damaged.

[0069] The ratio of force will vary according to materials anddimensions, but ratios of at least 2:1 permissible force to requiredforce are expected. If the percentage of the bump 61 which is raised 73is sufficient, higher ratios, such as 4:1, 10:1 and greater may beexpected. This is significant because variations in planarity may beexpected on the intermediate substrate 41 and the die 21.

[0070]FIG. 7 shows the use of a Z-axis anisotropic conductiveinterconnect material 77. The Z-axis anisotropic conductive interconnectmaterial 77 functions as an interface between the intermediate substrate41 and the bondpads or testpoints 27.

[0071] The Z-axis anisotropic conductive interconnect material 77 isparticularly useful in cases in which the bondpads 27 are recessed belowa BPSG passivation layer on the die 21. Other advantages of the Z-axisanisotropic conductive interconnect material 77 result from it beingeasily replaced when sequentially testing different dies 21 in the samepackage. The Z-axis anisotropic conductive interconnect material 77 isable to elastically deform in establishing ohmic contact with thebondpads 27, so that replacement or redoinking of the intermediatesubstrate 41 may be required less often.

[0072] By using the raised asperities 69 of FIG. 6 or the bumps 61 ofFIG. 6, the pressure applied against the die 21 and the bondpad 27 bythe Z-axis anisotropic conductive interconnect material 77 may becontrolled. It is anticipated that the Z-axis anisotropic conductiveinterconnect material 77 may be caused to selectively penetrate thebondpad 27 so that the Z-axis anisotropic conductive interconnectmaterial 77 will cause an indentation in the bondpad 27 which is lessthan the thickness of the bondpad 27. It is also anticipated that theremainder of the bondpad may be slightly distorted, but remains fullyworkable in subsequent assembly operations. The area of the bondpad 27where force is applied to establish ohmic contact by the Z-axisanisotropic conductive interconnect material 77 is thereby controlled bythe raised asperities 69 or by the topography of the bumps 61.

[0073] As can be seen in FIG. 7, the bondpads 27 are in some casesrecessed beneath the top surface of the die, as a result of theapplication of the passivation layer 53. The bondpads 27 also tend to befragile. If the Z-axis anisotropic conductive interconnect material 77is used to provide an interface between the bondpad 27 and theintermediate substrate 41, ohmic contact to be made through the Z-axisanisotropic conductive interconnect material 77, rather than directlybetween the intermediate substrate 41 and the bondpads 27. Conveniently,the Z-axis anisotropic conductive interconnect material is also able toextend between the intermediate substrate 41 and the contact pads 37,thereby also facilitating the connection of the intermediate substrate41 to the contact pads 37.

[0074] The use of the Z-axis anisotropic conductive interconnectmaterial 77 between the bondpads 27 and the intermediate substrate 41performs several functions. The ability of the Z-axis anisotropicconductive interconnect material to resiliently deform permits it todistort sufficiently to reach into the recesses defined by the bondpads27. The compliant nature of the Z-axis anisotropic conductiveinterconnect material 77 permits ohmic contact to be made with thebondpads 27 with a minimum of damage to the bondpads. This is importantin the burn in and testing of unpackaged die because it is desired thatthe bondpads remain substantially undamaged subsequent to burn in andtesting. The compliant nature of the Z-axis anisotropic conductiveinterconnect material 77 permits an intermediate contact member such asthe intermediate substrate 41 to be slightly misaligned with thebondpads 27. As long as there is a sufficient amount of material in theconductive path beneath the intermediate substrate 41 which is also incontact with the bondpads 27, ohmic contact will be established. It isalso necessary to provide a biasing force to maintain ohmic contact.While the biasing force may be achieved by using a further elastomericpad (79, shown in FIG. 9), the elastomeric nature of the Z-axisanisotropic conductive interconnect material 77 is also able to providesome biasing force.

[0075] Significantly, the Z-axis anisotropic conductive interconnectmaterial 77 need not be permanently bonded to the bondpads 27. Ohmiccontact is established by biasing force. This enables the Z-axisanisotropic conductive interconnect material 77 and intermediatesubstrate 41 to be lifted from the die 21 without destroying thebondpads 27.

[0076] The Z-axis anisotropic conductive interconnect material 77 andintermediate substrate 41 therefore are able to conduct signals betweenthe bondpads 27 and the die contacts 43.

[0077] It is also possible to permanently bond the Z-axis anisotropicconductive interconnect material 77 and the intermediate substrate 41 tothe die 21, and to retain the attachment to the intermediate substrate41 to the die 21 subsequent to burn in.

[0078] The cover 15 includes a rigid cover plate 81 and an optionalresilient compressible elastomeric strip 83, which serves as a resilientbiasing member, as shown in FIG. 8. When the cover plate 81 is securedto the die cavity plate 13, the elastomeric strip 83 biases the Z-axisanisotropic conductive interconnect material 77 and intermediatesubstrate 41 against the die 21. This establishes an ohmic contactbetween the bondpads 27 and the conductive traces on the intermediatesubstrate 41, without the intermediate substrate 41 being bonded to thebondpads 27.

[0079] It has been found that an optimum technique for temporarilysecuring the intermediate substrate 41 in place in the die cavity plate13 is the use of a precured RTV silicone strip, commonly known as “gelpack,” as a backing strip 85. The backing strip 85 exhibits a staticcharge sufficient and coefficient of friction sufficient to hold theintermediate substrate 41 in place without adhesive, and also iselastomeric. In other words, the silicone holds the silicon in place andbiases the silicon against the intermediate substrate 41 and cover plate81.

[0080] The elastomeric strip 83 is considered optional because it hasbeen found that an optimum technique for temporarily securing theintermediate substrate 41 in place in the die cavity plate 13 is the useof the precured RTV silicone strip as a backing strip 85. With the useof the backing strip 85, the die 21 therefore is biased against theintermediate substrate 41 even without the use of the elastomeric strip83, provided that the distances are appropriately selected to effectbiasing.

[0081] The non-bonded contact of the Z-axis anisotropic conductiveinterconnect material 77 is significant at the bondpads 27. Contactbetween the intermediate substrate 41 and the contact pads 37 on thefixture 11 may be effected by bonding techniques. Such bonding is notexpected to deteriorate the fixture 11, even though the fixture is usedmultiple times. If bonding is used for such contact, then the conductivematerial from the intermediate substrate may remain with the fixture 11,but without detriment to the operation of the fixture 11.

[0082] “Flip chip” optical alignment is used to align the cover plate 81with the die cavity plate 13. A clamp 89 then secures the cover plate 81in place over the die cavity plate 13. The clamp 89 may consist of awire clasp which may either be latched into place against itself, asshown, or is fitted into parallel horizontal locations in the die cavityplate 13 and the cover plate 81. With the cover plate 81 in place,conductors on the intermediate substrate 41 extend from the bondpads 27to the location of contact pads 37, so that the bondpads 27 are inelectrical communication with the external connector leads 33.

[0083] In the preferred embodiment, the clamp 89 is part of an external,cling system as described in U.S. patent Ser. No. 8/46,675, filed May14, 1993, entitled “CLAMPED CARRIER FOR TESTING OF SEMICONDUCTOR DIES”.This patent application is hereby incorporated by reference.

[0084] Providing the intermediate substrate 41 allows the die 21 isplaced face down, so as to establish connection between the bondpads 27and die contacts 43. The Z-axis anisotropic conductive interconnectmaterial 77 in this case is beneath the die 21. A precured RTV siliconebacking strip 95 is used to secure the die 21 to a cover plate 97 and tobias the die 21 against the die contacts 43.

[0085] In an alternate embodiment of a package 101, shown in FIG. 9, adie receiving housing 103 is used to retain a die 21 face up and anintermediate substrate 105 is placed above the die 21. The intermediatesubstrate 105 connects the die 21 to external test circuitry throughconnections on the die cavity housing. The die receiving housing 103contains a die receiving cavity 109, which supports the die 21 inalignment with electrical contacts 111 which align with bondpads 27 onthe die 21.

[0086] If Z-axis anisotropic conductive interconnect material 77 isused, the Z-axis anisotropic conductive interconnect material 77 ispositioned between the die 21 and the upper portion 105, so that theelectrical connection is established between the bondpads 27 and thecontacts 111, and hence with the connector pins 107.

[0087]FIG. 10 shows a configuration in which a housing fixture 141merely retains the die 21 in electrical communication with anintermediate substrate 143. The intermediate substrate 143 extendsbeyond the confines of the fixture 141 and terminates in an externalconnector 155. The Z-axis anisotropic conductive interconnect material77, if used, is positioned between the intermediate substrate 143 andthe die 21, so as to establish contact with the diepads 27.

[0088]FIG. 11 shows a configuration in which an intermediate substrate163 having conductors 165 is placed over a die 21. The die 21 is placedface up and bumps 167 on the substrate 163 face down to engage thebondpads 27. Advantageously, the substrate 163 may extend over thecontact pads 37 on the die cavity plate 13. A second set of bumps 168 onthe substrate 163 establish ohmic contact with the contact pads, whichelectrically connects the conductors 165 on the substrate 163 to thecontact pads 37.

[0089] While specific locations for bondpads had not been specified, itis possible to test a variety of configurations, including theconventional arrangement of bondpads at the ends of the die 21. Theinvention may also be used for testing die configured for LOC (leadsover chip), as well as other designs. In each of the above examples, theassembled fixture is adapted for testing with conventional testequipment, such as a burn-in oven. What has been described is a veryspecific configuration of a test fixture. Clearly, modification to theexisting apparatus can be made within the scope of the invention. Whilethe configuration of a standard DIP package has been shown in thedrawings, it is anticipated that other package configurations may beused. Other common configurations include PGA (pin grid array), LCC(leadless chip carrier) and MCR (molded carrier ring) packages, as wellas other package types. It is also likely that specialized package typeswill be used, in which the configuration relates to convenient burninand test handling. Accordingly, the invention should be read only aslimited by the claims.

1. A discrete testing apparatus for testing a semiconductor integratedcircuit device in die form, comprising: a) a first plate; b) adie-receiving cavity in the first plate; c) a second plate associatedwith the first plate; d) one of the first and second plates having aplurality of connector terminals thereon; e) a die attachment surfacelocated within the die receiving cavity, the die attachment surfacehaving a plurality of circuit traces extending therefrom, the circuittraces extending to contacts to establish electrical communication withcontact locations on the die; f) the plurality of contacts beingpositioned so that, when the die is positioned in the die-receivingcavity, the contacts are in alignment with contact locations on the dieand extending to the contact locations; g) the plurality of contactsbeing formed with at least one raised portion, the raised portionextending sufficiently that it may penetrate its respective contactlocation on the die, thereby establishing electrical communication withsaid contact location, said extension of the raised portion beinglimited so that, when a force is applied to the raised portion issignificantly less than a force required for portions of the contactsoutside of the raised portion to penetrate its respective contactlocation, thereby limiting a penetration depth of the bump contacts atthe contact location; and h) the connector terminals in electricalcommunication with the contacts, the connector terminals being mountedto the one of said plates.
 2. A discrete testing apparatus as describedin claim 1 , further comprising: said one raised portion extending so asto penetrate to less than ⅔ of a thickness of its respective contactlocation on the die.
 3. A discrete testing apparatus as described inclaim 1 , further comprising: said one raised portion extending so as topenetrate to less than ½ of a thickness of its respective contactlocation on the die.
 4. A discrete testing apparatus as described inclaim 1 , further comprising: said one raised portion extending so as topenetrate to less than ⅔ of a thickness of its respective contactlocation on the die and said one raised portion extending at least 5000Å.
 5. A discrete testing apparatus as described in claim 1 , furthercomprising: the die attachment surface being formed of semiconductormaterial, and the circuit traces being formed on the semiconductormaterial by semiconductor circuit fabrication techniques.
 6. A discretetesting apparatus as described in claim 5 , further comprising: the dieattachment surface being of a thickness sufficient to be substantiallyrigid.
 7. A discrete testing apparatus as described in claim 5 , furthercomprising: the die attachment surface being sufficiently thin to bepartially flexible.
 8. A discrete testing apparatus as described inclaim 5 , further comprising: the die attachment surface being formed ofa structure which includes silicon material, and the circuit tracesbeing formed on the silicon material by semiconductor fabricationtechniques.
 9. A discrete testing apparatus as described in claim 8 ,further comprising: the die attachment surface being of a thicknesssufficient to be substantially rigid.
 10. A discrete testing apparatusas described in claim 8 , further comprising: the die attachment surfacebeing sufficiently thin to be partially flexible.
 11. A discrete testingapparatus as described in claim 1 , further comprising: a) the dieattachment surface being formed of a ceramic insulator, and the circuittraces being formed on a surface of the substrate; and b) the dieattachment surface having s aid plurality of circuit traces formedthereon extending from the contacts to connection points on said one ofthe first and second plates having a plurality of contacts thereon. 12.A discrete testing apparatus as described in claim 1 , furthercomprising: a) the die attachment surface being formed of a ceramicinsulator, and the circuit traces being formed on a surface of thesubstrate; b) the die attachment surface having said plurality ofcircuit traces formed thereon extending from the contacts to connectionpoints on said one of the first and second plates having a plurality ofcontacts thereon; and c) the die attachment surface being sufficientlythin to be partially flexible.
 13. A discrete testing apparatus asdescribed in claim 1 , further comprising: the die attachment surfacebeing positioned in the die receiving cavity so that the plurality ofcontacts on the die attachment surface face away from the first plate,wherein the die is positioned above the die attachment surface with thecontact locations on the die facing the die receiving cavity.
 14. Adiscrete testing apparatus as described in claim 1 , further comprising:the die attachment surface being positioned in the die receiving cavityso that the plurality of contacts on the die attachment surface face arein a face up position with respect to the die receiving cavity and thedie is positioned above the die attachment surface with the contactlocations in a face down position on the die facing the die receivingcavity.
 15. A discrete testing apparatus as described in claim 1 ,further comprising: the die being positioned in the die receiving cavityso that the contact locations on the die are in a face up position withrespect to the plurality of contacts on the die attachment surface andthe die attachment surface is positioned above the die with theplurality of contacts in a face down position on the die attachmentsurface the die receiving cavity.
 16. A discrete testing apparatus asdescribed in claim 1 , further comprising: a pad which is electricallyconductive in a Z-axis, normal to a plane of the pad, and which provideselectrical isolation across the plane of the pad, the pad beingpositioned between the die and the plurality of contacts.
 17. A discretetesting apparatus as described in claim 1 , further comprising: a) aresilient pad to bias die received in the die receiving cavity with thecontacts after the first and second plates have been mated, to applysufficient pressure to maintain ohmic contact between said substrate andsaid contact locations on the die; and b) said contacts cooperating withsaid pad to apply sufficient pressure between said pad and said contactlocations on the die to establish ohmic contact with said contactlocations on the die.
 18. A discrete testing apparatus as described inclaim 1 , further comprising: an elastomeric strip further securing thesubstrate in a position within the die receiving cavity by means ofelectrostatic attraction and frictional forces, thereby permitting thesubstrate to be maintained in a positional alignment with respect to thedie receiving cavity after being placed into the die receiving cavityand prior to mating the second plate with the first plate.
 19. Adiscrete testing apparatus as described in claim 1 , further comprising:an elastomeric strip further securing the die in a position within thedie receiving cavity by means of electrostatic attraction and frictionalforces, thereby permitting the die to be maintained in a positionalalignment with respect to the die receiving cavity after being placedinto the die receiving cavity and prior to mating the second plate withthe first plate.
 20. A discrete testing apparatus as described in claim1 , further comprising: a) first and second plates biasing the dietoward the die attachment surface in order to establish said electricalcommunication of the contacts with the contact locations on the die; b)the second plate being secured to the first plate by a clamp, the clampapplying biasing pressure for said biasing of the die toward the dieattachment surface; and c) said contacts cooperating with said first andsecond plates and said clamp to apply sufficient pressure between saidpad and said contact locations on the die to establish ohmic contactwith said contact locations on the die.
 21. A discrete testing apparatusfor testing a semiconductor device in die form, comprising: a) a firstplate; b) a die-receiving cavity in the first plate; c) a second plate;d) means to secure the first and second plates together; e) an dieattachment surface having a plurality of conductors thereon anddimensioned so as to fit within the testing apparatus adjacent to thedie when the die is in the die receiving cavity; f) a pad which iselectrically conductive in a Z-axis, normal to a plane of the pad, andwhich provides electrical isolation across the plane of the pad, the padbeing positioned over the die between the die and the plurality of dieattachment surface; and g) a plurality of contacts on the plurality ofconductors, the contacts being positioned so that, when the first plateand the second plate are aligned by the alignment means and the die andthe die attachment surface are positioned in the die-receiving cavity,the contacts are in alignment with contact locations on the die; h)connector terminals in an electrical communication with the plurality ofcontacts; and i) a support to hold the die, the pad, and the dieattachment surface together when the first plate and the second plateare secured together, wherein when the first and second plates aresecured together with the die in the die receiving cavity, a pluralityof said contact locations are in electrical communication with theconnector terminals, and the plurality of contacts result in the Z-axisconductive pad causing a portion of the pad to establish ohmic contactwith said contact locations, said contacts being formed so that, when aforce is applied to the contact is significantly less than a force whichwould cause the Z-axis conductive pad to significantly damage thecontact location at locations where said ohmic contact is notestablished.
 22. A discrete testing apparatus as described in claim 21 ,further comprising: the die attachment surface being formed of astructure which includes silicon material, and the circuit traces beingformed on the silicon material by semiconductor fabrication techniques.23. A discrete testing apparatus as described in claim 22 , furthercomprising: the die attachment surface being of a thickness sufficientto be substantially rigid.
 24. A discrete testing apparatus as describedin claim 22 , further comprising: the die attachment surface beingsufficiently thin to be partially flexible.
 25. A discrete testingapparatus as described in claim 21 , further comprising: a) the dieattachment surface being formed of a ceramic insulator, and the circuittraces being formed on a surface of the substrate; and b) the dieatttachment surface having said plurality of circuit traces formedthereon extending from the contacts to connection points on said one ofthe first and second plates having a plurality of contacts thereon. 26.A discrete testing apparatus as described in claim 21 , furthercomprising: the die attachment surface extending beyond the confines ofa fixture formed by the first and second plates and terminating in anexternal connector, the external connector including said connectorterminals.
 27. A discrete testing apparatus as described in claim 21 ,further comprising: means, separate from said pad, to bias the diereceived in the die receiving cavity with the die attachment surfaceafter the first and second plates have been mated, the means to biascooperating with said pad to apply sufficient pressure between said padand said contact locations on the die to establish ohmic contact betweensaid pad and said contact locations on the die.
 28. A discrete testingapparatus as described in claim 27 , further comprising: the means tobias comprising an elastomeric polymer.
 29. A discrete testing apparatusfor testing a semiconductor device in die form, comprising: a) a firstplate; b) a die-receiving cavity in the first plate; c) a second plate;d) means to secure the first and second plates together; e) an dieattachment surface having a plurality of conductors thereon anddimensioned so as to fit within the testing apparatus adjacent to thedie when the die is in the die receiving cavity; f) a pad which iselectrically conductive in a Z-axis, normal to a plane of the pad, andwhich provides electrical isolation across the plane of the pad, the padbeing positioned over the die between the die and the plurality of dieattachment surface; and g) a plurality of contacts on the plurality ofconductors, and formed with at least one raised portion, the contactsbeing positioned so that, when the first plate and the second plate arealigned by the alignment means and the die and the die attachmentsurface are positioned in the die-receiving cavity, the contacts are inalignment with contact locations on the die; h) connector terminals inan electrical communication with the plurality of contacts; and i) asupport to hold the die, the pad, and the die attachment surfacetogether when the first plate and the second plate are secured together,wherein when the first and second plates are secured together with thedie in the die receiving cavity, a plurality of said contact locationsare in electrical communication with the connector terminals, and theraised portions on the plurality of contacts resulting in the Z-axisconductive pad causing a portion of the pad to establish ohmic contactwith said contact locations, said extension of the raised portion beinglimited so that, when a force is applied to the raised portion issignificantly less than a force which would cause the Z-axis conductivepad to significantly damage the contact location at locations where saidohmic contact is not established.
 30. A discrete testing apparatus asdescribed in claim 21 , further comprising: the die attachment surfacebeing formed of a structure which includes silicon material, and thecircuit traces being formed on the silicon material by semiconductorfabrication techniques.
 31. A discrete testing apparatus as described inclaim 30 , further comprising: the die attachment surface being of athickness sufficient to be substantially rigid.
 32. A discrete testingapparatus as described in claim 30 , further comprising: the dieattachment surface being sufficiently thin to be partially flexible. 33.A discrete testing apparatus as described in claim 21 , furthercomprising: a) the die attachment surface being formed of a ceramicinsulator, and the circuit traces being formed on a surface of thesubstrate; and b) the die attachment surface having said plurality ofcircuit traces formed thereon extending from the contacts to connectionpoints on said one of the first and second plates having a plurality ofcontacts thereon.
 34. A discrete testing apparatus as described in claim21 , further comprising: the die attachment surface extending beyond theconfines of a fixture formed by the first and second plates andterminating in an external connector, the external connector includingsaid connector terminals.
 35. A discrete testing apparatus as describedin claim 21 , further comprising: means, separate from said pad, to biasthe die received in the die receiving cavity with the die attachmentsurface after the first and second plates have been mated, the means tobias cooperating with said pad to apply sufficient pressure between saidpad and said contact locations on the die to establish ohmic contactbetween said pad and said contact locations on the die.
 36. A discretetesting apparatus as described in claim 35 , further comprising: themeans to bias comprising an elastomeric polymer.
 37. A package for asemiconductor integrated circuit device in die form, comprising: a) ahousing b) a substrate within said housing, the substrate having aplurality of circuit traces extending therefrom, the circuit tracesextending to contacts to establish electrical communication with contactlocations on the die, the circuit traces extending to contacts toestablish electrical communication with contact locations on the die; c)the plurality of contacts being formed with at least one raised portion,the raised portion extending sufficiently that it may penetrate itsrespective contact location on the die, thereby establishing electricalcommunication with said contact location, the plurality of contactsbeing formed with at least one raised portion, the raised portionextending sufficiently that it may penetrate its respective contactlocation on the die, thereby establishing electrical communication withsaid contact location, said extension of the raised portion beinglimited so that, when a force is applied to the raised portion issignificantly less than a force required for portions of the contactsoutside of the raised portion to penetrate its respective contactlocation, thereby limiting a penetration depth at the contact location;d) connector terminals in electrical communication with the contacts,the connector terminals extending from said housing; and e) theconnector terminals in electrical communication with the contacts.
 38. Apackage as described in claim 37 , further comprising: a) the connectorterminals being located on said substrate; and b) said substrateextending beyond the confines of said housing.
 39. A package asdescribed in claim 37 , further comprising: a) the contacts being formedas raised asperities; and b) the asperities being formed by doinkingmaterial which is deposited on the substrate.
 40. A package as describedin claim 37 , further comprising: a) the contacts formed as bumps on thesubstrate, with raised portions on the bumps; and b) the raised portionsbeing dimensioned such that they readily penetrate the contact locationson the die, while the remainder of the bump functions to limitpenetration depth of the raised portion.
 41. A package as described inclaim 37 , further comprising: a pad which is electrically conductive ina Z-axis, normal to a plane of the pad, and which provides electricalisolation across the plane of the pad, the pad being positioned betweenthe die and the plurality of raised portions, wherein the raisedportions on the plurality of contacts result in the Z-axis conductivepad causing a portion of the pad to establish ohmic contact with saidcontact locations, said extension of the raised portion being limited sothat, when a force is applied to the raised portion is significantlyless than a force required to cause the Z-axis to damage the contactlocation at locations where said ohmic contact is not established.
 42. Adiscrete testing apparatus as described in claim 1 , further comprising:said one raised portion from a level of a passivation layer on thesemiconductor die to an extent sufficient to extend into its respectivecontact location on the die, wherein the penetration of the raisedportion into the contact location on the die is controlled by the dieattachment surface resting against the passivation layer.
 43. A discretetesting apparatus as described in claim 1 , further comprising: said oneraised portion from a level of a passivation layer on the semiconductordie to an extent sufficient to extend into its respective contactlocation on the die, wherein the penetration of the raised portion intothe contact location on the die is controlled by the plurality ofcontacts resting against the passivation layer.